1. Field of the Invention
Example embodiments of the present invention relate to semiconductor devices, for example, semiconductor devices and/or random access memories (RAMS) having a fin-type channel region. For example, semiconductor devices according to at least one example embodiment of the present invention may include a FinFET, and a RAM according to at least one example embodiment of the present invention may include a DRAM, an RRAM, a FeRAM and/or a NOR-type flash memory.
2. Description of the Related Art
FinFETs may use an upper surface and side surfaces of a fin as a channel region. Therefore, FinFETs may have a channel area wider than that of a planar-type transistor and may provide increased current flow. As a result, the FinFET may provide higher performance as compared to planar-type related art transistors.
However, related art FinFET are fabricated using, for example, an SOI substrate, and the fin may float from a substrate body. The floating fin may increase the difficulty of controlling a threshold voltage of a transistor using body-bias and/or controlling a threshold voltage of a CMOS transistor. As a drain depletion region is expanded using a related art bulk substrate, a junction leakage current, an off-current and/or a junction capacitance may be increased. A threshold voltage may be reduced in more highly-integrated devices using a short channel effect; however, this may increase off-current.
Related art FinFETs may also have a higher contact resistance. For example, a related art FinFET may include bit line contacts formed to run across fins. In this example, because the bit line contacts and the narrow surfaces of the fins are in contact, a bit line contact resistance may increase. Furthermore, fabrication may be more difficult because the fins may be bent when forming the bit line contacts.
According to the related art, source and drain regions may be formed to connect to fins and/or formed wider to help ensure a contact area. However, a distance between the fins may become wider due to the source and drain regions, and integration density of a FinFET may be reduced.